1. Field of the Invention
The present invention relates to a constant voltage generating circuit, and more specifically to a constant voltage generating circuit having a step-up circuit.
2. Description of Related Art
One example of this type constant voltage generating circuit is disclosed in Japanese Patent Application Laid-open Publication JP-A-4-372571. Referring to FIG. 1A, there is shown a circuit equivalent to the constant voltage generating circuit disclosed in this publication JP-A-4-372571, which is modified to have a step-up circuit composed of an increased number of elements so as to be compared with embodiments of the present invention explained hereinafter. This constant voltage generating circuit comprises a step-up circuit 50, a clamp circuit 60a, a voltage detecting circuit 70a and a clock control circuit 80a.
The step-up circuit 50 includes a series-connected N-channel MOSFETs (gate-insulated field effect transistor) 51 to 55 each of which has a drain electrode and a gate electrode interconnected to each other and which are connected between a voltage supply voltage terminal 92 (Vdd) and a high voltage output terminal 100 (Vpp). A gate-drain connecting node of each of the N-channel MOSFETs 52 and 54 is connected through a capacitor 56 or 58 to an output of an inverter I.sub.51, and a gate-drain connecting node of each of the N-channel MOSFETs 53 and 55 is connected through a capacitor 57 or 59 to an output of an inverter 152. An input of the inverter I.sub.51 is connected to a clock input terminal 94 (.phi..sub.5), and an input of the inverter I.sub.52 is connected to the output of the inverter I.sub.51. With this arrangement, a high voltage Vpp is generated with a clock signal .phi..sub.5 applied to the clock input terminal 94.
The clamp circuit 60a includes a P-channel MOSFET 61 having a gate connected to the voltage supply voltage terminal 92 (Vdd) and a source electrode connected to the high voltage output terminal 100 (Vpp), and an N-channel MOSFET 62 having a drain connected to a drain of the P-channel MOSFET 61, a gate connected to the voltage supply voltage terminal 92 (Vdd) and a source electrode connected to ground.
The voltage detecting circuit 70 is composed of an inverter I.sub.71 having an input connected to a connection node B between the P-channel MOSFET 61 and the N-channel MOSFET 62.
The clock control circuit 80a has a NAND gate N.sub.81 having one input connected to an external clock terminal 96 (.phi.) and the other input. connected to an output line D of the inverter I.sub.71. An output of the NAND gate N.sub.81 is connected to the clock input terminal 94 (.phi..sub.5).
Now, operation of the above mentioned constant voltage generating circuit will be described with reference to FIG. 1B.
When a step-up operation is started, since a potential Vpp on the high voltage output terminal 10 is at a low level, the P-channel MOSFET 61 in the clamp circuit 60a is off, and therefore, the node B is pulled down by the N-channel MOSFET 62. Since a voltage V.sub.B on the node B is at a low level, the output line D of the inverter I.sub.71 is at a high level, and therefore, the clock signal .phi. supplied to the external clock terminal 96 is supplied through the NAND gate N.sub.81 to the clock input terminal 94 as an internal clock .phi..sub.5. Thus, the step-up circuit 50 is put into operation, so that electric charge is supplied to the high voltage output terminal 100 and therefore, the potential Vpp on the high voltage output terminal 100 is rising up.
When the potential Vpp on the high voltage output terminal 100 elevates to a clamp voltage Vcl (=Vdd+.vertline.Vtp.vertline., where Vtp is a threshold voltage of the P-channel MOSFET 61), the P-channel MOSFET 61 is turned on so that the potential V.sub.B on the node B is brought into a high level. Accordingly, the potential on the output line D of the inverter I.sub.71 becomes the low level (which constitutes a voltage detection signal), and the output .phi..sub.5 of the NAND gate N.sub.81 is brought into a high level.
Accordingly, the clock signal .phi. supplied to the external clock terminal 96 is not transmitted to the clock input terminal 94, and therefore, the step-up circuit 50 stops its operation.
As mentioned above, the constant voltage generating circuit shown in FIG. 1A is configured to detect that the potential Vpp on the high voltage output terminal 100 elevates to the clamp voltage Vcl, and to stop the step-up circuit 50 in response to the voltage detection signal, so that a wasteful operation of the step-up circuit after the voltage elevation has been completed is prevented so as to reduce a consumed electric power, and also to prevent generation of noises.
Incidentally, in the constant voltage generating circuit shown in FIG. 1A, when the voltage elevation is completed and therefore when the operation of the step-up circuit 50 is stopped, the elevation of the potential Vpp on the high voltage output terminal 100 stops, so that the P-channel MOSFET 61 is turned off. Therefore, the potential V.sub.B on the node B is pulled down by the N-channel MOSFET 62 and drops below a logical threshold voltage of the inverter I.sub.71.
Accordingly, the potential of the output line D of the inverter I.sub.71 is brought to the high level, so that the clock signal .phi. is supplied through the NAND gate N.sub.81 to the clock input terminal 94, and therefore, the step-up circuit 5 starts its operation again. As a result, the potential Vpp on the high voltage output terminal 100 elevates to the clamp voltage, and the voltage detection signal D is outputted again so as to stop the operation of the step-up circuit 50. These operations are repeated during each voltage elevating period.
Another example of this type constant voltage generating circuit is disclosed in Japanese Patent Application Laid-open Publication JP-A-62-197998. Referring to FIG. 2A, there is shown the constant voltage generating circuit disclosed in this publication JP-A-62-197998, which comprises a step-up circuit 50, a clamp circuit 60b, a voltage detecting circuit 70b and a clock control circuit 80b. In FIG. 2A, elements corresponding to those shown in FIG. 1A are given the same Reference Numerals, and explanation thereof will be omitted.
The clamp circuit 60b includes N-channel MOSFETs 63 to 66 which are connected in series between the high voltage output terminal 100 (Vpp) and the ground and each of which has a drain and a gate interconnected to each other.
The voltage detection circuit 70b includes an inverter I.sub.72 having an input connected to a connection node E between the N-channel MOSFETs 65 and 66, and another inverter I.sub.73 having an input connected to an output of the inverter I.sub.72.
The clock control circuit 80b includes a frequency-division circuit 81 having an input connected to the external clock terminal 96 (.phi.), a NAND gate N.sub.83 having a first input connected to the external clock terminal 96 (.phi.) and a second input connected to receive an output F of the inverter I.sub.73 through an inverter I.sub.81, another NAND gate N.sub.84 having a first input connected to an output of the frequency-division circuit 81 and a second input connected to the output F of the inverter I.sub.73, and still another NAND gate N.sub.82 having a first input connected to an output of the NAND gate N.sub.83 and a second input connected to an output of the NAND gate N.sub.84, an output of the NAND gate N.sub.82 being connected to the clock input terminal 96 (.phi.).
The step-up circuit 50 is similar to that shown in FIG. 1A, and therefore, explanation thereof will be omitted.
Now, operation of the constant voltage generating circuit shown in FIG. 2A will be explained with reference to FIG. 2B.
When the voltage elevating operation is started, a potential Vpp on the high voltage output terminal 100 is at a low level, and only an off current flows through the series-connected N-channel MOSFETs 63, 64, 65 and 66 in the clamp circuit 60b. Therefore, a potential V.sub.E on the node E is pull down to a threshold V.sub.TN of the N-channel MOSFET 66 by action of the N-channel MOSFET 66, and accordingly, a potential on the output line F of the inverter I.sub.73 is at a low level. As a result, the clock signal .phi. applied from the external clock terminal 96 is supplied through the NAND gates N.sub.83 and N.sub.82 to the clock input terminal 94 as an internal clock .phi.6, and therefore, the step-up circuit 50 starts to operate, so that electric charge is supplied to the high voltage output terminal 100, and accordingly, the potential Vpp on the high voltage output terminal 100 is elevating.
With the above voltage elevating operation, when the potential Vpp on the high voltage output terminal 100 reaches a clamp voltage Vcl (=4.times.V.sub.TN, where V.sub.TN is a threshold of the N-channel MOSFETs 63 to 66), the N-channel MOSFETs 63 to 65 are turned on so that the potential V.sub.E on the node E is pulled up to a high level, and the potential on the output line F of the inverter I.sub.73 is brought to a high level. Accordingly, the clock signal .phi. applied to the external clock terminal 96 is frequency-divided to one fourth of the frequency of the external clock by the frequency-division circuit 81, and the frequency-divided clock signal is supplied through the NAND gates N.sub.84 and N.sub.82 to the clock input terminal 94 as the internal clock .phi.6. As a result, the step-up circuit 50 operates with the frequency-divided, namely, low frequency, clock signal.
As mentioned above, the constant voltage generating circuit shown in FIG. 2A is configured to detect that the potential Vpp on the high voltage output terminal 100 elevates to the clamp voltage Vcl, and to supply the frequency-divided, low frequency, dock signal to the step-up circuit 50 in response to the voltage detection signal, so that a consumed electric power of the step-up circuit after the voltage elevation is reduced and generation of noises is prevented.
In ordinary cases, however, to the high voltage output terminal 100 is connected a load including not only a capacitive component CL and a resistive component RL caused by a wiring conductor resistance, as illustrated in FIG. 3.
In the conventional constant voltage generating circuit shown in FIG. 1A, since the voltage Vpp on the high voltage output terminal 100 is detected, when the high voltage output terminal 100 is connected to a load including a resistive component RL shown in FIG. 3, an output current Ipp flowing out from the high voltage output terminal 100 pulsates in synchronism with the clock signal .phi..
Therefore, as shown in FIG. 1B, an overshoot occurs on the potential Vpp on the high voltage output terminal 100, so that when a peak of this overshoot voltage reaches the clamp voltage Vcl, the voltage detection signal is generated, with the result that the clock signal .phi. becomes not transmitted to the clock input terminal 94 (.phi..sub.5), and therefore, the step-up circuit 50 stops its operation.
Thereafter, the potential Vpp on the high voltage output terminal 100 drops by a voltage of the overshoot component, since the electric charge is transferred through the resistive component RL to the capacitive component CL of the load. Accordingly, although the potential on the overshoot is lower than the clamp voltage Vcl, the elevation of the potential Vpp on the high voltage output terminal 100 stops.
The voltage of the overshoot component is defined by Ipp.times.RL. Since the output current Ipp flowing in response to the clock signal is on the order of 10 mA at maximum, if the resistive component RL caused by the wiring conductor resistance is on the order of 100 .OMEGA., the voltage of the overshoot component becomes 1 V. Accordingly, the voltage elevation stops with Vpp=Vcl-1 (V).
After the voltage elevation stops, the potential V.sub.B on the node B is pulled down by means of the N-channel MOSFET 62 and gradually lowers. At the moment the potential V.sub.B on the node B lowers smaller than the threshold voltage of the inverter I.sub.71, the clock signal is supplied to the step-up circuit 50 again, and the step-up circuit 50 re-starts its operation.
Thus, the potential Vpp on the high voltage output terminal 100 elevates to the clamp voltage Vcl for the first time. As a result, a period of time Tup required for a necessary voltage elevation becomes extremely long.
Here, it may be considered that the factor "gm" of the N-channel MOSFET 62 is set to a large value, so that the pull-down of the potential V.sub.B on the node B is speeded up, with the result that the period of time Tup for the voltage elevation is shortened. In this approach, however, the operation in which after the step-up circuit 50 stops its operation because of the completion of the voltage elevation, the potential on the node B is pulled down, and then, the step-up circuit 50 is caused to re-start its operation, is repeated at short intervals. This results in an increased consumed power and in increase of the noises.
Furthermore, after the voltage V.sub.B on the node B becomes the high level, the voltage V.sub.B on the node B is pulled down through the N-channel MOSFET 62 and therefore gradually lowers. Accordingly, the input of the inverter I.sub.71 (constituting the voltage detection circuit 70a) is biased an intermediate level for a long period of time, so that a pass-through current flows in the inverter I.sub.71. As a result, the consumed electric power is increased, and a voltage supply noise and ground noise are induced.
Also in the conventional constant voltage generating circuit shown in FIG. 2A, since the voltage Vpp on the high voltage output terminal 100 is detected similarly to the conventional constant voltage generating circuit shown in FIG. 1A, when the high voltage output terminal 100 is connected to a load including a resistive component RL shown in FIG. 3, a period of time Tup required for a necessary voltage elevation becomes extremely long as shown in FIG. 2B.
In the conventional constant voltage generating circuit shown in FIG. 2A, it is possible to shorten the period of time Tup for the voltage elevation, by setting the frequency-division ratio, for example, to 1/2 in place of 1/4. In this approach, however, since the operating frequency after the completion of the voltage elevation is not set to a low value, both of the consumed electric power and the generation of the noise are increased.
In addition, since the potential V.sub.E on the node E is Vpp-3 V.sub.TN, in the case that the load capacitance is large and therefore the voltage elevation velocity of the high voltage output terminal is low, the input of the inverter I.sub.72 (constituting the voltage detection circuit 70b) is biased at an intermediate level for a long period of time, so that a pass-through current flows in the inverter I.sub.72. As a result, the consumed electric power is increased, and both of a voltage supply noise and ground noise are induced.
As mentioned above, since the conventional constant voltage generating circuits shown in FIGS. 1A and 2A are so constructed to detect the potential Vpp on the high voltage output terminal 100, these conventional circuits are disadvantageous in that when a load including a resistive component is driven, it is not possible to simultaneously realize both the shortening of the period of time Tup for the voltage elevation and the reduction of the consumed electric power and the noise generation.
Furthermore, since the input of the inverter constituting the voltage detection circuit is biased at an intermediate level for a long period of time, a pass-through current flows in the inverter, with the result that the consumed electric power is increased, and both of a voltage supply noise and ground noise are induced.